Cache memory has been conventionally used in a computer system. The cache memory may predict that data used by a central processing device (CPU) may be soon used again, for example, and hold the data in high-speed cache memory so that the data can be quickly accessed. The cache memory may therefore overcome the restrictions of the access speed of main memory.
However, computer systems have had multiple cores, and a pipeline processing system has been used as an access system to cache memory. As a result, the congestion of a pipeline has become serious and required a workaround to the reduction of the congestion.
FIG. 1 is an explanatory view of a conventional pipeline control system using a multi-core system. In FIG. 1, an MI (move-in)-PORT is a port for storing a command as a new request transmitted from, for example, each core of the multi-core system. In response to the command stored in the port, the priorities are determined among the commands output from each core at the stage of a PR (priority) 1. Then, at the stage of a PR2, the priorities of commands are determined among other ports, that is, an MO (move-out)-PORT storing a response from a core to cache and move-out data from a core, and an SC-PORT storing an order provided from a system controller (SC). The commands are sequentially put in the stages of the pipeline for access processing from a command having a higher priority, that is, from the XP0 to the XP6. The commands that have passed through the pipeline are output to an external interface unit of the CPU as a request SC-REQ for a system controller.
In the prior art above, in addition to an essential command requiring access to cache memory when the command is executed, a command not requiring access to the cache memory such as a command for a write or a read of data to and from an ASI (address space identify) register has been provided for an external interface unit through a pipeline from the XP0 to the XP6 illustrated in FIG. 1. Accordingly, the more numbers of cores in a multi-core system and commands to be processed, the more problems of the congestion in the pipeline will occur.
Patent document 1 as the prior art relating to the control of cache memory described above discloses a technique of accessing at a high speed a part of an area in main memory specified as a noncache area using no cache memory by switching a bus to a bypass route for providing address and data output from an MPU directly to main memory when an address in a bus is within a predetermined address range.
Next, Patent document 2 discloses a technique of improving a use efficiency of cache memory by checking the value of a frequency of accessing a memory position not in the cache from a processor, executing access to the cache if the value exceeds a threshold, and bypassing the cache if the value does not exceed the threshold.    Patent Document 1: Japanese Laid-open Patent Publication No. 2-32436 “Buffer Storage Device”    Patent Document 2: Japanese Patent Publication No. 2735781 “Cache Memory Control System and Method”
However, the conventional techniques above cannot solve the problem that the congestion in a pipeline largely increases in a multi-core system having an increasing number of cores when all commands including those not accessing cache memory during the execution of commands are to pass through the pipeline for cache memory access.